1. Field of Invention
The present invention relates to a semiconductor memory, more particularly, to a write recovery time control circuit and a control method thereof which provides sufficient write recovery time between a write and a read operation.
2. Discussion of Related Art
Input data signals having been latched to a data input buffer of a DRAM are transferred to a data bus line by write control signals. A write buffer charges or discharges the data bus line up to a VCC voltage level or down to a VSS voltage level in accordance with logic values of these input data signals.
In a fast page mode, after a write operation, the next read or write operation of new data is executed shortly thereafter. Accordingly, a write path or a read path of data must be recovered promptly by removing the data signals carried by the data bus line.
A time necessary for initializing the data bus line is called a write recovery time. When the write recovery time increases, operation speed decreases because of the longer time required to initialize the data bus line.
FIG. 1 shows a conventional circuit of an address decoder in semiconductor memory. The above-mentioned write recovery time is established by delaying a time, after a write operation, at which a corresponding word line is selected and subsequently activated by a new address to read data.
Referring to FIG. 1, the row address decoder is comprised of a least significant bit (hereinafter abbreviated LSB) decoder 101 and an address decoder 102. These two decoders act as a main decoder which activates a word line selection signal of a corresponding address by means of decoding a predecoded address signal generated from a predecoder (not shown). The generation of a predecoded address signal using a predecoder is well-known in the art and will not be described.
In the LSB decoder 101, a cell block address signal Z and a LSB X0 of a predecoded address signal, having bits X0 to X3, from the predecoder are decoded. For ease of description, a predecoded address signal of four bits is shown in FIG. 1. An address signal decoded by the LSB decoder 101 results in a power control signal which controls an output stage of the address decoder 102. As is known, the cell block address signal Z comes from decoding a portion of the lower bits of a row address. As shown in FIG. 1, the LSB decoder 101 includes a first NAND gate 103, receiving the block address signal Z and the bit X0 as inputs, and a first inverter 104 connected to the output of the first NAND gate 103.
The address decoder 102 decodes the bits X1 to X3 of the predecoded address signal. The address decoder 102 includes a plurality of decoding modules 150-1, 150-2, . . . , 150-N, each of which is comprised of two AND gates (NAND+Inverter) that are connected in parallel.
The constitution of the address decoder 102 is explained in the following description wherein the decoding modules 150-1 to 150-N receive combinations of bits X1, X2, and X3, from the predecoded address signal, and bits `/X1, /X2, /X3` (i.e., the inverses of X1, X2, and X3).
First, bits /X1 to /X3 are inputted to a second NAND gate 105. When the logic value of the original predecoded address signal bits X1 to X3 are `0`, the logic values of the inverted signals /X1 to /X3 become `1`. Thus, the output of the second NAND gate 105 is `0`.
The logic value `0` output from the second NAND gate 105 is inverted by a second inverter 106. One input terminal of a two input third NAND gate 107 is directly supplied with the output of the second inverter 106, while the other terminal is supplied with the output of the second inverter 106 through a delaying unit 110.
In this case, a low level output of the third NAND gate 107 is somewhat delayed due to the delaying unit 110. The delaying unit 110 includes third and fourth inverters 108 and 109 connected in series. The low level output of the third NAND gate 107 is inverted by fifth and sixth inverters 123 and 124 connected in parallel. Thus, the fifth and sixth inverters 123 and 124 produce two word line selection signals.
The fifth inverter 123 is controlled by the power control signal, while the sixth inverter 124 is controlled by an inverted power control signal. Accordingly, only one of the fifth and sixth inverters 123 and 124 activates the word line selection signal.
When a power control signal outputted from the first inverter 104 of the LSB decoder 101 has a low level, the fifth inverter 123 of the address decoder 102 turns on. Thus, a first word line selection signal becomes activated. On the other hand, when the power control signal has a high level, the sixth inverter 124 turns onto activate a second word line selection signal.
By connecting two inverters in parallel and having one of the two inverters turn on based on a power control signal, two word line selection signals will be generated from the first decoding module 150-1.
The other decoding modules 150-2 to 150-N, have the same structure as the first decoding module 150-1, but receive a different combination of the bits X1, X2 and X3 and their inverses.
Each of the decoding modules 150-1 to 150-N has a delaying unit to delay when a word line selection signal is activated. Delaying when the word line selection signal is activated means that a fixed time interval lies between a time when a new address is input and a time when a selected word line corresponding to a designated address is activated. The time interval is the write recovery time.
However, as a single address decoder includes a plurality of decoding modules and each of the decoding modules has a delaying units, the size of each delaying unit should be identical to ensure a precise write recovery time.
If even one of the sizes of the delaying units differs in size from another, it is difficult to set up a precise timing of a read or a write operation of the memory because the write recovery time becomes somewhat variable.
In order to overcome the above problem and perform a stable read/write operation of the memory, a sufficient margin is built into the write recovery time.
Unfortunately, this means the write recovery time takes longer than is necessary. It is very disadvantageous when trying to perform a fast operation that a time for reading new data takes longer due to the write recovery time being longer than necessary. Moreover, it is hard to achieve a high chip density because many delaying units are required.